The present specification generally relates to analog-to-digital converters (ADCs) and particularly to differential non-linearity corrections in ADCs using a look-up table.
Analog-to-digital converters (ADCs) employ a variety of different circuit techniques to implement the conversion function. One of the popular techniques used for moderate to high-speed application is the successive-approximation type ADC shown in FIG. 1.
The operation of this ADC is analogous to weighing an unknown object on a laboratory balance scale as 1, 1/2, 1/4, 1/8, . . . 1/n standard weight units. The largest weight is placed on the balance pan first; if it does not tip, the weight is left on and the next largest weight is added. If the balance does tip, the weight is removed and the next one added. The same procedure is used for the next largest weight and so on down to the smallest. After the n-th standard weight has been tried and a decision made, the weighing is finished. The total of the standard weights remaining on the balance is the closest possible approximation to the unknown weight.
In the ADC illustrated in FIG. 1, a successive-approximation register 100 controls the digital-to-analog converter (DAC) 102 by implementing the weighing logic with successively smaller size capacitors. However, even though the capacitors are scaled relative to one another, there are often errors in the scaling. A differential non-linearity (DNL) can occur based on errors in the relationship of the sizes and capacities of the capacitors.
An array of ADCs are used in digital imaging devices, such as active pixel sensor (APS) cameras, include many sensors arranged into arrays of columns and rows. Each image sensor collects electrical charge when exposed to light. Control signals provided to the image sensors periodically enable the sensors to transfer the collected charges to the array of ADCs. The collected charges are converted to digital data and stored in the column-parallel ADC registers.